For almost four decades, the integration density in microelectronics has been following “Moore's Law,” which states a doubling approximately every 18 months, with simultaneous halving of the production costs. Traditionally, the production of microelectronic products has been divided into the so-called front end (essentially application and structuring of thin films on wafers) and, after these are sawed into individual chips, the so-called back end (assembly of the chips on carriers, electrical contacting, and enclosure or enveloping).
The mechanical and electrical connections of the chip to the carrier are brought together into a single step with the flip-chip technique. In this way, significant miniaturization and better signal transmission due to low inductance values is made possible by means of this connection technique.
The combination of flip-chip assembly with a utilization technique in which a plurality of chips is mounted on a common carrier is particularly advantageous. In this manner, components are now being implemented whose footprint does not exceed the actual chip area required for active structures and connections by more than 20%, with the term chip sized package (CSP) being commonly used for this.
Lateral chip dimensions of approximately 1 mm are below dimensions where conventional housings (“tub” with lid) could be used. For these reasons, leading semiconductor manufacturers have developed packaging concepts in recent years, which provide for encapsulation on the wafer level, i.e., before individualization of the components, after wafer structuring.
A true wafer level packaging avoids the individual handling of individual chips. With this, the implementation of a true CSP is made possible even with very small chip dimensions. Fundamentally, all the housing functionalities can be implemented on the wafer level. Aside from the protection against mechanical and climatic influences, as well as the provision of electrical connections that are compatible with industry standards such as surface assembly and re-flow solders, re-wiring can also take place here, for example. In this connection, chip connectors can be freely positioned on the outside housing surface. This is made possible by means of one or more insulation layers, interfacial connections, and conductive structures. Internal connections are also possible in this manner.
The demand for true CSP is further emphasized by the pressure towards miniaturization and, to a particular degree, in the case of expensive substrates (e.g., LiTaO3, GaAs).
For semiconductor components that do not require any housing cavity, on the basis of their method of functioning, there are a large number of appropriate concepts. Some of them have already become so broadly established that they are offered on the packaging of specialized service providers. An example is the method known under the trademark UltraCSP.
A fundamental technical problem of all solutions paths that have been proposed until now is the long-term reliability of the components, since the internal and external connections become fatigued due to temperature change stress. This must particularly be taken into account by means of coordinating the thermal expansion properties of the materials used.
The stated task is made even more difficult as soon as the demand for a housing cavity for the component structures is added, for example in the case of SAW (surface acoustic wave) components. Often, a hermetic seal in the sense of a diffusion seal of this cavity is also demanded, since otherwise the resistance to damp heat can be insufficient, resulting in corrosion, problems caused by condensate on active structures, problems with the moisture content of polymers used in soldering processes, etc.). A hermetic seal can fundamentally not be achieved with polymer-based molding masses, resins, or adhesives, since these materials are more or less permeable for gases and moisture, due to permeation processes.
In WO2000/3508A1, an active structure on a wafer is surrounded with a frame of photoresist, for example, onto which a circuit board is glued as a cover. Interfacial connections guide the electrical connectors from the chip to contacts on the circuit board. No sufficient hermetic seal is achieved with the sealing layer that covers the back of the chip as well as the side surfaces of the component, since the circuit board is not completely covered, because the usual resin laminates with fiber reinforcement recommended as the sealing layer are particularly disadvantageous in terms of their diffusion seal, since moisture can spread along the border layer between the polymer and the fibers. However, the decisive disadvantage is that the sealing layer described can no longer be applied on the wafer level, but only afterwards, on the individual component.
From WO2001/4318A1, another method for packaging is known. Here, the wafer is glued between two covers. Frame-shaped spacers define a cavity above the active chip structure, if necessary. The electrical contacts run around the chip to contacts (110) on the back cover, by means of metal structures that were originally produced on the wafer and those that are structured in sawed notches along the separation lines (108). The joining materials are polymers, with which no diffusion seal can be achieved, as was explained. The concept does not permit complete metallization (and therefore a seal), since the electrical connections require several metal structures that are electrically separated from one another.
It is therefore the task of the present invention to indicate a simple and cost-effective method for true CSP, on the wafer level, for SAW filters and other components, with which method components having a diffusion seal can be produced.